Canon CS-S 4.3 Specifications download pdf (Page 18)

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3.2 Register Detail

Note: Some data formats are given as (S/U # of integer bits. # of fractional bits). For

example, S1.3 means the value can be either positive or negative with the first bit indicating

the sign, one integer bit and three fractional bits. U0.8 means no sign bit (positive number),

zero integer bits and eight fractional bits. Negative values must be programmed as 2’s

complement. A format of Bn means a binary format with n bits used.

Address : 400x0 (CNTL1)

Data format : B15

Default Value: 00h

15 14 13 12 11 10 9 8

Not used OUTFMT[3:0] LUTEN

7 6 5 4 3 2 1 0

IMRST TRGSNS VIDEN HTRIG STRBM[1:0] TRIGM[1:0]

TRIGM: Trigger Mode. These bits control the trigger source as well as trigger operation.

TRIGM[1:0] = 00 : Local Trigger, One Shot

TRIGM[1:0] = 01 : Local Trigger, Retriggerable

TRIGM[1:0] = 10 : Host Trigger, One Shot

TRIGM[1:0] = 11 : Host Trigger, Retriggerable

Local Trigger: Trigger is input directly to camera via external connector.

Host Trigger: Trigger is issued via 1394 interface.

One Shot: Edge on trigger input initiates one video frame.

Retriggerable: Repeats Frames as long as trigger input is active. Time between

frames controlled by RTGDLY register.

When in one-shot mode, integration time can be controlled by the FPGA, the

IBIS sensor or the trigger duration. The control for this is located in Control

using an external trigger.

Trigger Mode TRIGM[1:0] IBMODE[1:0] (Control

Reg 2)

Trigger mode A (IIDC Trigger Mode

00b 10b Use FPGA register to

control integration time.

Trigger mode B (IIDC Trigger Mode

00b 11b Use trigger duration to

control integration time.

Trigger mode C 01b 01b Use sensor register to

control integration time.

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Canon CS-S 4.3 Specifications Page 18